1. Field of the Invention
The present invention relates to the field of integrated electronic circuit technology. More particularly, the invention relates to a reliable and manufacturable selectively formable vertical diode circuit element (hereinafter "element"). The element of the present invention may be applied to a Programmable Read Only Memory (PROM) cell in an array with a high packing density, a field programmable logic array, PLA (PLD), and in general to any application requiring a programmable PN junction interconnect element.
2. The Prior Art
It is known to form a connection to an already-manufactured diode element by using one of many known programmable interconnect elements. The prior art does not teach forming a diode junction during the process of forming an interconnect element. Examples of the prior art include U.S. Pat. No. 3,576,549.
In addition, Read Only Memory (ROM) devices have been commonly used to store programs in computer systems. Mask programmed ROMs are the lowest in cost in high volume production, but have the disadvantage of long lead time to manufacturing and an initial high design fee. Programmable ROMs (PROMs) have the advantage of being field programmable by the user. The most-often-used PROMs for high-speed applications are bipolar PROMs which use bipolar fusible link or vertical shorting junction elements. Bipolar PROMs are used in high speed applications but are expensive to manufacture due to their large cell size needed to accommodate the fusible link and its associated selection device in addition to the higher cost of manufacturing using a bipolar technology process.
For instance, because of the nature of the conducting material in the link, relatively high current levels are needed to blow the fusible links during programming. Also, the shape and size of the fusible link must be precise so that the link will function effectively as a conductor if it is not blown and will be a completely open circuit if it is blown. Therefore, very critical photolithographic steps and controlled etch techniques are required during the manufacturing process of fusible link PROMs. Finally, a large gap must be blown in the link in order to prevent it from later becoming closed through the accumulation of the conducting material near the blown gap. Fusible link memory cells are relatively large in order to accommodate the link and, therefore, fusible link PROM devices have high manufacturing and material costs and take up large amounts of chip area.
Other EPROMs use floating gate technology and have a more compact cell size than bipolar PROMs. However, the floating gate EPROM technology has a complicated process flow and depends on data retention in the floating gate which is vulnerable to loss of data by leakage or radiation. In addition floating gate EPROM's are slower than bipolar PROMs because of their high cell resistance, resulting in lower cell reading current.
Various PROM memory cells have been proposed such as: U.S. Pat. Nos. 3,634,929 and 4,499,557, where the anti-fuse is a capacitor and the selection element is an isolated diode, and U.S. Pat. Nos. 4,322,822 and 4,507,757 where the anti-fuse is a capacitor and the selection element is an MOS transistor. In both these disclosures, and all other prior art known to the inventors, the selection device is fabricated prior to programming.
All of the prior art methods known to the inventors as illustrated by the aforementioned patents create a large memory cell and/or require a more complex process because of the need to have both the anti-fuse and the selection element fabricated before programming.